sod-923 shipping 8000/tape&reel s esd9l5.0t5 ordering information device marking d 1 2 esd protection diodes with ultra ? low capacitance the 6esd9l is designed to protect voltage sensitive components that require ultra ?low capacitance from esd and transient voltage events. excellent clamping capability, low capacitance, low leakage, and fast response time, make these parts ideal for esd protection on designs where board space is at a premium. because of its low capacitance, it is suited for use in high frequency designs such as usb 2.0 high speed and antenna line applications. specification features: ? ultra low capacitance 0.5 pf ? low clamping voltage ? small body outline dimensions: 0.039 x 0.024 (1.00 mm x 0.60 mm) ? low body height: 0.016 (0.4 mm) ? stand? off voltage: 5 v ? low leakage ? response time is typically < 1.0 ns ? iec61000? 4 ? 2 level 4 esd protection ? this is a pb? free device mechanical characteristics: case: void-free, transfer-molded, thermosetting plastic epoxy meets ul 94 v ? 0 lead finish: 100% matte sn (tin) qualified max reflow temperature: device meets msl 1 requirements pin 1. cathode 2. anode 12 maximum ratings rating symbol value unit iec 61000 ? 4 ? 2 (esd) contact air 10 15 kv total power dissipation on fr ? 5 board (note 1) @ t a = 25 c p d 150 mw storage temperature range t stg ? 55 to +150 c junction temperature range t j ? 55 to +125 c lead solder temperature ? maximum (10 second duration) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. fr ?5 = 1.0 x 0.75 x 0.62 in. 260 c peak pulse current i pp peak power dissipation p pk 8 x 20 sec. 8 x 20 sec. 5(max) 50(max) a w willas electronic corp. 2012-09 sesd9l5.0t5 ?
electrical characteristics (t a = 25 c unless otherwise noted) symbol parameter i pp maximum reverse peak pulse current v c clamping voltage @ i pp v rwm working peak reverse voltage i r maximum reverse leakage current @ v rwm v br breakdown voltage @ i t i t test current i f forward current v f forward voltage @ i f p pk peak power dissipation c capacitance @ v r = 0 and f = 1.0 mhz *see application note and8308/d for detailed explanations of datasheet parameters. uni?directional tvs i pp i f v i i r i t v rwm v c v br v f electrical characteristics (t a = 25 c unless otherwise noted, v f = 1.0 v max. @ i f = 10 ma for all types) device device marking v rwm (v) i r ( a) @ v rwm v br (v) @ i t (note 2) i t c (pf) v c (v) @ i pp = 1 a (note 3) v c max max min ma typ max max per iec61000 ? 4 ? 2 (note 4) sesd9l5.0t5 d 5.0 1.0 5.4 1.0 0.5 0.9 9.8 figures 1 and 2 see below 2. v br is measured with a pulse test current i t at an ambient temperature of 25 c. 3. surge current waveform per figure 5. 4. for test procedure see figures 3 and 4 and application note and8307/d. figure 1. esd clamping voltage screenshot positive 8 kv contact per iec61000 ?4?2 figure 2. esd clamping voltage screenshot negative 8 kv contact per iec61000 ?4 ?2 willas electronic corp. 2012-09 esd protection diodes with ultra ? low capacitance sesd9l5.0t5
iec 61000 ?4?2 spec. level test voltage (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000? 4 ? 2 waveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 3. iec61000 ?4?2 spec figure 4. diagram of esd test setup 50 50 cable tvs oscilloscope esd gun the following is taken from application note and8308/d ? interpretation of datasheet parameters for esd devices. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000 ? 4 ? 2 waveform. since the iec61000?4? 2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d. figure 5. 8 x 20 s pulse waveform 100 90 80 70 60 50 40 30 20 10 0 02 04 06 08 0 t, time ( s) % of peak pulse current t p t r pulse width (t p ) is defined as that point where the peak current decay = 8 s peak value i rsm @ 8 s half value i rsm /2 @ 20 s willas electronic corp. 2012-09 esd protection diodes with ultra ? low capacitance sesd9l5.0t5
sod?923 0.40 0.30 0.90 dimensions: millimeters soldering footprint* willas electronic corp. 2012-09 esd protection diodes with ultra ? low capacitance sesd9l5.0t5 . 0 3 0 ( 0 . 7 5 ) . 0 3 3 ( 0 . 8 5 ) .006(0.15) .010(0.25) .022(0.55) .026(0.65) .013(0.34) .017(0.43) .037(0.95) .041(1.05) .003(0.07) .007(0.17) dimensions in inches and (millimeters)
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